The metal-oxide semiconductor field effect transistor (MOSFET) is a dominant and important device in fabricating very large-scale integrated circuits, and various types of MOSFETS are known. MOSFET technology basically can be categorized as consisting of NMOS and CMOS technology, the former comprising n-channel MOS devices and the latter comprising n-channel and p-channel devices integrated on the same chip. Other acronyms are used to identify MOSFETs, including DMOS (wherein "D" stands for "diffusion" or "double diffusion"), PMOS (p-channel MOS), IGBT (Insulated Gate Bipolar Transistor), BiCMOS (CMOS having bipolar devices), and DGDMOS (Dual Gate DMOS). Following accepted terminology, the term CMOS denotes that n-channel and p-channel devices are integrated simultaneously on the same chip, and the term CMOS is so used herein.
Various types of semiconductor devices, as well as both n-channel and p-channel devices, may be integrated within a single semiconductor chip. This is made possible by use of device structures and processes which are compatible with the different types of devices included on the chip. However, designing the devices to achieve compatibility typically means that performance of each of the devices will be less than optimal. CMOS devices provide significant advantages in terms of their low power consumption, but they generally require more complex processing as compared with NMOS devices. Also, with present technology, CMOS structures have been confined to low voltage devices operable at less than 5V. N-channel DMOS or IGBT devices operating at medium (10-100) and high (&gt;100) voltages may be made to be complementary with p-channel DMOS devices, but presently this is achieved by separately fabricating the complementary p-channel devices, using different processing steps, which then may be coupled to the n-channel devices. These are not CMOS devices in that they are not integrated simultaneously on one chip.
To illustrate, referring to FIG. 1A, there is shown a cross-sectional view of a prior art n-channel MOS device, without double diffusion. The characteristic features of this basic device comprise a p-type semiconductor substrate 12 having a major surface 14, within which are disposed two n+ regions or bodies 16a, 16b, forming a source and drain, respectively. Overlying the surface 14 is a gate electrode 20, typically fabricated with polysilicon or a combination of polysilicon and silicide (MoSi.sub.2), separated from surface 14 by a layer of gate oxide 22. Field oxide layer 24 isolates the source and drain, and a protective layer of glass 34, typically boron phosphorus silicate glass, is disposed over the device. A further silicon nitride layer (not shown), may be disposed over the glass. The channel 23 is defined by the upper portion of the substrate 12, which underlies gate 20. FIG. 1A shows an n-channel device (NMOS), but a p-channel device (PMOS) may be formed following the same schematic by substituting p for n and reversing the polarity of the charges.
FIG. 1B illustrates a basic CMOS structure involving NMOS and PMOS devices integrated on the same chip, following the structure for the MOS of FIG. 1A and using like character numerals to refer to like features. Metallization region 35, typically fabricated with aluminum, may be deposited over the device and etched as desired (as shown), for interconnection of the device structures. The gate of the NMOS device 30 may be connected to the gate of the PMOS device 40. For example, a conductive conduit 38, having contact V.sub.G, is shown schematically with hatched lines interconnecting the gates. In processing this CMOS, a p-tub or well 18 is implanted in the n-substrate, enabling formation of the complementary devices in substrate 12. Separate implantation steps are required for forming the p-tub 18, the n+ source and drain regions 16a, 16b, and the p+ source and drain regions 16c, 16d; p-type regions generally are formed by implantation with boron ions, and n-type regions by implantation with arsenic or phosphorus ions. Because of the p-tub 18 and the processing needed to make the PMOS, the number of steps for fabricating the basic CMOS of FIG. 1B is essentially double that for the NMOS of FIG. 1A.
Referring now to FIG. 2A, there is shown a basic embodiment of a double-diffused, n-channel MOS, again with like numerals used to refer to like features as compared with FIGS. 1A-1B. Substrate 12 of n-type conductivity is disposed within a chip 100 and isolated from it by a layer of dielectric material 102, such as silicon dioxide. The substrate 12 has a major surface 14 on which active components are disposed, e.g., gate electrode 20 insulated by gate oxide layer 22. The device here shown comprises spaced-apart, plural source regions connected in parallel. Source regions comprise first doped regions 17 of n-type conductivity, connected by source electrodes 21, and second doped regions 19 of p-type conductivity formed within substrate 12. A region of p+ type conductivity 25 may be implanted beneath source contacts 21, interposed between each of the doped bodies comprising the source regions, as also described in U.S. Pat. No. 5,541,429, "Dielectrically Isolated Semiconductor Devices Having Improved Characteristics," issued Sep. 17, 1996 to M. A. Shibib, the inventor herein, assigned to AT&T Corp., a predecessor of the assignee herein, which is incorporated herein by reference.
The second doped regions 19 extend further laterally under gate electrode 20 than first doped regions 17. The portions 23 of the second doped regions 19 extending beyond the first regions 17 beneath the gate oxide comprise the channel regions of the device, and the substrate beneath the surface portion comprises a drain region. Also, a doped body 26 of n+ conductivity forms a supplemental drain region in contact with drain electrode 27. A heavily-doped region 28 may extend laterally along the bottom of the substrate and then vertically upwardly to drain electrode 27. This channel 28 provides a low resistance path for current to the drain electrode for controlling the current as the DMOS devices typically are used in applications involving high voltages and currents.
The Insulated Gate Bipolar Transistors (IGBT) can be identical to the DMOS devices illustrated in FIG. 2A, except that certain high conductivity regions are of opposite type conductivity to that of the substrate 12. For example, FIG. 3A shows a prior art n-channel IGBT device, wherein doped regions 76, 77 are of opposite conductivity to the substrate. Further background concerning MOS devices and the various structures that may be used can be found in the following U.S. patents, all of which issued to the inventor herein, Muhammed Ayman Shibib, were assigned to the present assignee or its predecessor in interest, and are hereby incorporated herein by reference: U.S. Pat. No. 5,670,396, "Method of Forming a DMOS Controlled Lateral Bipolar Transistor," issued Sep. 23, 1997; U.S. Pat. No. 5,557,125, "Dielectrically Isolated Semiconductor Devices Having Improved Characteristics," issued Set. 17, 1996; U.S. Pat. No. 5,541,409, cited above; U.S. Pat. No. 5,395,776, "Method of Making a Rugged DMOS Device," issued Mar. 7, 1995; U.S. Pat. No. 5,381,031, "Semiconductor Device With Reduced High Voltage Termination Area and High Breakdown Voltage," issued Jan. 10, 1995. Bipolar CMOS devices are further described in M. Ayman Shibib & G. T. Jones, "A Cost Effective Smart Power BiCMOS Technology," Proceedings of 1995 International Symposium on Power Semiconductor Devices & IC (1995) (hereinafter the "Symposium article"), also incorporated herein by reference.
As should now be appreciated from the foregoing, fabricating doubly-diffused p-channel devices complementary to n-channel DMOS and IGBT devices involves complicated processing steps. A CMOS such as illustrated in FIG. 1B may be fabricated by implantation or diffusion of the doped regions in the n-type substrate. However, while compatible, this CMOS would not be self-aligned or double-diffused. This results in a less efficient device and need for a larger device to achieve the same performance parameters than if the complementary p-channel device were double-diffused.
Present technology does not permit for fabrication of double-diffused CMOS devices, i.e., double-diffused n- and p-channel devices simultaneously integrated on the same chip, and therefore, CMOS devices have not been available for high voltage applications. Generally, CMOS devices are available for applications of up to 5 volts. As applied to MOS devices in general and as used herein, 0 to 10 volts is considered low voltage; 10 to 100 volts is considered medium voltage; and devices operating at above 100 volts are considered high voltage devices.
Complementary DMOS and IGBT structures may be built on separate chips and interconnected, but fabricating complementary p-channel structures involves processes and technologies differing from those used for the n-channel DMOS and IGBT structures. To make a p-channel device complementary to an n-channel DMOS device, typically the fabrication processes are reversed on a separate chip, that is, instead of an n-type substrate, a p-type substrate is used. An n-well or tub may be implanted or infused into the substrate, and p+ bodies are implanted into the n-well. While this produces a double-diffused, efficient device operating at medium or high voltage, the process is time consuming. Efforts have been made to integrate the fabrication of DMOS and CMOS devices on the same chip. See, e.g., U.S. Pat. No. 5,171,699, "Vertical DMOS Transistor Structure Built in an N-Well CMOS-Based BiCMOS Process and Method of Fabrication," issued Dec. 15, 1992 to Hutter et al., assigned to Texas Instruments, Inc.; U.S. Pat. No. 5,374,569, "Method for Forming a BiCDMOS," issued Dec. 20, 1994 to Yilmaz et al., assigned to Siliconix Inc.; U.S. Pat. No. 5,591,657, "Semiconductor Apparatus Manufacturing Method Employing Gate Side Wall Self-Aligning for Masking," issued Jan. 7, 1997, to Fujishima et al., assigned to Fuji Electric Co., Ltd; all three of the immediately foregoing patents are hereby incorporated by reference.
Additionally, a further drawback with present CMOS technologies involving DMOS devices, beyond the need to use separate chips and technologies, involves use of the p-type base regions. P-type substrates are expensive to form and often call for processing steps incompatible with standard fabrication procedures which are generally based upon n-well implantation processes. Thus, it would be advantageous to provide a double-diffused CMOS having p- and n-channel devices disposed on an n-type region which may be easily fabricated based on available technology.
The invention has utility for better optimizing the features of various devices in integrated circuits of the type described above and in reducing the processing steps for fabricating a variety of MOS and bipolar complementary devices. The invention provides a cost-effective method of fabricating a complementary high voltage MOS and bipolar structure on the same chip and with the same substrate as a DMOS of opposite-type conductivity. Further advantages may appear more fully upon considering the description given below.